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<a href="#define-members">Macros</a> &#124;
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Macros</h2></td></tr>
<tr class="memitem:ga816dc349df40d377cb0b08d93bee37d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips__v3__2.html#ga816dc349df40d377cb0b08d93bee37d2">XQspiPs_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;XQspiPs_In32((BaseAddress) + (RegOffset))</td></tr>
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<tr class="memitem:ga0d50616771e04824af465a0f078a7ebb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips__v3__2.html#ga0d50616771e04824af465a0f078a7ebb">XQspiPs_WriteReg</a>(BaseAddress,  RegOffset,  RegisterValue)&#160;&#160;&#160;XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td></tr>
<tr class="separator:ga0d50616771e04824af465a0f078a7ebb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets from the base address of an QSPI device. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Configuration Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains various control bits that affect the operation of the QSPI device.</p>
<p>Read/Write. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">QSPI Interrupt Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p><b>QSPI Status Register</b></p>
<p>This register holds the interrupt status flags for an QSPI device. Some of the flags are level triggered, which means that they are set as long as the interrupt condition exists. Other flags are edge triggered, which means they are set once the interrupt condition occurs and remain set until they are cleared by software. The interrupts are cleared by writing a '1' to the interrupt bit position in the Status Register. Read/Write.</p>
<p><b>QSPI Interrupt Enable Register</b></p>
<p>This register is used to enable chosen interrupts for an QSPI device. Writing a '1' to a bit in this register sets the corresponding bit in the QSPI Interrupt Mask register. Write only.</p>
<p><b>QSPI Interrupt Disable Register </b></p>
<p>This register is used to disable chosen interrupts for an QSPI device. Writing a '1' to a bit in this register clears the corresponding bit in the QSPI Interrupt Mask register. Write only.</p>
<p><b>QSPI Interrupt Mask Register</b></p>
<p>This register shows the enabled/disabled interrupts of an QSPI device. Read only.</p>
<p>All four registers have the same bit definitions. They are only defined once for each of the Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, and Channel Interrupt Status Register </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Enable Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to enable or disable an QSPI device.</p>
<p>Read/Write </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Delay Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to program timing delays in slave mode.</p>
<p>Read/Write </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Slave Idle Count Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register defines the number of pclk cycles the slave waits for a the QSPI clock to become stable in quiescent state before it can detect the start of the next transfer in CPHA = 1 mode.</p>
<p>Read/Write </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Transmit FIFO Watermark Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register defines the watermark setting for the Transmit FIFO. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Receive FIFO Watermark Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register defines the watermark setting for the Receive FIFO. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">FIFO Depth</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This macro provides the depth of transmit FIFO and receive FIFO. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Linear QSPI Configuration Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains various control bits that affect the operation of the Linear QSPI controller.</p>
<p>Read/Write. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Linear QSPI Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains various status bits of the Linear QSPI controller.</p>
<p>Read/Write. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Loopback Delay Adjust Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains various bit masks of Loopback Delay Adjust Register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">SLCR Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Bit Masks of above SLCR Registers . </p>
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Functions</h2></td></tr>
<tr class="memitem:ga2732af9facd00339b5dc96c83d74a355"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips__v3__2.html#ga2732af9facd00339b5dc96c83d74a355">XQspiPs_ResetHw</a> (u32 BaseAddress)</td></tr>
<tr class="separator:ga2732af9facd00339b5dc96c83d74a355"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad769e09710e28c9876cebf678f6e890c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips__v3__2.html#gad769e09710e28c9876cebf678f6e890c">XQspiPs_LinearInit</a> (u32 BaseAddress)</td></tr>
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